PD (partially depleted)-SOI (silicon-on-insulator)-CMOS (complementary metal oxide semiconductor) technology has significant speed, power and radiation immunity advantages over bulk CMOS technology. However, it has been difficult to manage the floating body effect (FBE) of SOI devices. One problem associated with PD-SOI-CMOS devices involves an unstable body potential over a range of frequencies. Thus, PD-SOI-CMOS technology has yet to be widely accepted by the systems and design communities.
In bulk NMOSFET devices, for example, the body often is tied to a fixed potential or to the source of the device However, the body potential in NMOSFET-SOI is floating and remains unstable due to the complex dynamics of hole generation at the drain edge, and with carrier recombination and diffusion. Several undesirable characteristics results from FBE, such as “Kink Effect” (current enhancement) in Id-Vg characteristics of the device, enhanced leakage due to parasitic (npn) bipolar (BJT) current, and enhanced 1/f noise. These effects restrict the ability to design complex circuits and the range of applications for SOI technology. Circuit-related issues attributable to FBE include threshold instability, hysteretic behavior in signal input/output, frequency-dependent pulse delays, and signal pulse width modulation.
In logic design, FBE can lead to data loss, dynamic circuit failure and timing delays. Additionally, FBE can limit analog circuit applications due to transistor mismatch and enhanced AC/DC noise.
One proposed solution for suppressing FBE involves Field Shield Isolation technology. Another proposed solution for suppressing FBE involves Bipolar Embedded Source Structure (BESS). Another proposed solution for suppressing FBE involves SI—Ge Inserted SOI. Another proposed solution for suppressing FBE involves SOI devices with implanted recombination centers. Another proposed solution involves Schottky body-contacted SOI.
These proposed solutions reduce parasitic effects by regulating body potential but do not provide frequency independent device threshold. Therefore, these proposed solutions are limited in scope since the floating body potential is time dependent and the body potential at any instant is the transient result of multiple mechanisms of widely differing time constants. If the body potential could be regulated such that it is time-independent (i.e. frequency independent), and could be accurately predicted, the body potential could be utilized to significantly enhance circuit performance and complex circuit design.
Additionally, in the current state-of-the-art associated with bulk silicon technology, complex circuit and system designs require the use of design simulators, tools, and methodology in which embedded device models accurately predict device thresholds within a wide range of operating frequencies at all design and application conditions (viz. geometry, doping profile, temperature, node potential etc).
However, these simulators, tools and methodology are not available for SOI technology due to the time-dependent threshold of the floating body SOI device.
Therefore, there is a need in the art to provide improved PD-SOI-CMOS devices and fabrication methods that ensures frequency-independent device threshold by means of providing frequency independent body potential.